FIG. 7 is a diagram showing an example of a conventional loaded line phase shifter formed on a semiconductor substrate, and FIG. 8 is a diagram showing an equivalent circuit of the loaded line phase shifter shown in FIG. 7. In FIG. 7, reference numeral 1 denotes a semiconductor substrate formed of silicon, GaAs, or the like, and 2 denotes a grounding conductor formed on the bottom surface of the semiconductor substrate 1 by a metallization such as gold. Reference numeral 3 denotes a main line of the loaded line phase shifter, and reference numerals 18 denote corrected lines loaded to the main line 3 with a spacing of approximately one-quarter wavelength. Reference numerals 5a and 5b denote drain electrodes of field effect transistors (referred to as FETs hereinafter), 6a and 6b denote gate electrodes of the FETs, and reference numeral 19 denotes a common source electrode of the two FETs. The drain electrode 5a, the gate electrode 6a, and the source electrode 19 constitute an FET 8a, and the drain electrode 5b, the gate electrode 6b, and the source electrode 19 constitute an FET 8b. Reference numerals 9a and 9b denote high impedance lines approximately one-quarter wavelength long, 10a and 10b denote low impedance lines approximately one-quarter wavelength long, and 11a and 11b denote bias pads for receiving external driving bias voltages. The high impedance line 9a, the low impedance line 10a, and the bias pad 11a constitute a distributed constant bias circuit 12a, and the high impedance line 9b, the low impedance line 10b, and the bias pad 11b constitute a distributed constant bias circuit 12b. Reference numeral 13 denotes a high impedance line approximately one-quarter wavelength long, 14 denotes a low impedance line approximately one-quarter wavelength long, and 15 denotes a grounding pad. The high impedance line 13, the low impedance line 14, and the grounding pad 15 constitute a grounding bias circuit 16 which is connected to the main line 3. In addition, reference numeral 20 denotes a gold wire for grounding the source electrode 19, 24 denotes an input terminal, and 25 denotes an output terminal.
In the loaded line phase shifter having the above described structure, the same driving bias voltage must always be applied to the two FETs 8a and 8b. This driving bias voltage is switched to forward bias (zero volt) or reverse bias (minus several volts) to change the impedances of the FETs 8a and, 8b and therefore, to change the susceptance of the loaded lines 18 viewed from the main line 3. The loaded line phase shifter exercises control such that the difference in transmission phases becomes a desired value. The grounding conductor 2 is grounded by soldering into a chassis or the like. The driving bias voltage is applied to the gate electrodes 6a and 6b from the distributed constant bias circuits 12a and 12b, respectively. In order to normally operate the FETs 8a and 8b, the common source electrode 19 is grounded by the gold wire 20 or the like and the drain electrodes 5a and 5b are grounded by grounding the grounding pad 15 using a gold wire or the like, so that the common electrode 19 and the drain electrodes 5a and 5b are set at the same voltage level as the grounding conductor 2.
When the driving bias voltage is a forward bias, the FETs 8a and 8b are on, so that the FET is brought to a resistance of several ohms. Accordingly, in this case, the impedance of the FET viewed from nodes of the main line 3 and the loading lines 18 becomes inductive. On the other hand, when the driving bias voltage is the reverse bias, the FETs 8a and 8b are off, so that the FET appears as a capacitance between the source electrode with the drain electrode and a parallel-connected resistance of several kilo-ohms. Accordingly, in this case, the impedance of the FET portion viewed from the nodes of the main line 3 and the loading lines 18 becomes capacitive.
As described in the foregoing, the bias voltage applied to the gate electrodes 6a and 6b is changed to make the FETs 8a and 8b inductive stubs or capacitive stubs, thereby changing the phase of a wave propagating along the main line 3.
In the conventional loaded line phase shifter formed on a semiconductor substrate, however, the susceptance values of the two loaded lines 18 are respectively changed using the different FETs 8a and 8b as described above. Accordingly, variations in characteristics between the two FETs 8a and 8b introduce the problem that phase characteristics and insertion loss characteristics or the like of the phase shifter are degraded so that the desired phase shift characteristics cannot be obtained.
FIG. 9 shows an example of a loaded line phase shifter constructed to make variations in characteristics between the FETs as small as possible in consideration of the above described problem. More specifically, FIG. 9 is a circuit diagram showing a loaded line phase shifter in another conventional example which is disclosed in Japanese published Patent Application 59-51602, and FIG. 10 is a diagram showing an equivalent circuit of the loaded line phase shifter shown in FIG. 9. In FIGS. 9 and 10, the same reference numerals as those in FIGS. 7 and 8 refer to the same elements. Reference numeral 21 denotes a penetrating conductor 21 for grounding a source electrode 19, 22 denotes a capacitor connected to both gate electrodes 6a and 6b, and 23 denotes a bias circuit having its end connected to the capacitor 22. This loaded line phase shifter is arranged such that the source electrode 19 is common to two FETs 8a and 8b and connected to respective end terminals of loaded lines 18. The loaded lines 18 are connected to the main line 3 with a spacing of one-quarter wavelength. This arrangement makes the FETs 8a and 8b as similar to each other as possible. In addition the common source electrode 19 is connected to a grounding conductor 2 by the penetrating conductor 21 to decrease variations in characteristics between the FETs. In addition, the capacitor 22 is connected to both the gate electrodes 6a and 6b and the bias circuit 23 is connected to one end of the capacitor 22 to apply a bias voltage to the gate electrodes 6a and 6b.
In the loaded line phase shifter having this structure, the bias voltage applied to the gate electrodes 6a and 6b through the bias circuit 23 is changed to change the susceptance of the connected lines 18 loaded to the main line 3 with spacing of one-quarter wavelength, thereby changing the phase of a wave propagating along the main line 3, as in the above described loaded line phase shifter in the first conventional example.
In the above described structure, the FETs 8a and 8b are disposed in close proximity to each other at one end of each of the loading lines 18. Accordingly, the loaded line phase shifter has the advantage that variations in characteristics between the FETs 8a and 8b can be prevented, as compared with the above described loaded line phase shifter in the first conventional example shown in FIG. 7. In addition, a single bias circuit is used for determining the bias voltage applied to the gate electrodes 6a and 6b. Accordingly, the loaded line phase shifter has the advantage that the bias circuit can be simplified.
In the structure of the loaded line phase shifter in the above described second conventional example, variations in characteristics between the FETs 8a and 8b can be decreased but cannot be completely eliminated. Furthermore, in the above described both first and second conventional examples, the source electrode 19 must be grounded. Consequently, various problems arise. More specifically, in the first conventional example, the source electrode 19 is grounded by the gold wire 20. Accordingly, variations in the inductive component of the gold wire 20 on the entire phase shifter are produced by non-uniformities in the length of the gold wire 20 so that the phase characteristics of the phase shifter are changed. These variations increase insertion loss and the voltage standing wave ratio (referred to as VSWR hereinafter) of the phase shifter. In addition, the source electrode 19 must be formed at an end of a substrate in order to minimize these problems in the performance of the phase shifter due to the inductance component of the gold wire 20, limiting pattern design.
Furthermore, in the second conventional example, the source electrode 19 is grounded using the penetrating conductor 21. Also in this case, the induction component of the penetrating conductor 21 cannot be ignored, thereby presenting the same problem as that in the first conventional example. In addition, although the degree of freedom in pattern design is increased, complicated manufacturing processes are required to form the penetrating conductor 21.